ChipForge
A modular AI-driven chip design toolkit: Python packages for spec, HDL, verification, synthesis, place-and-route, agents, a CLI and a dashboard, wrapping Yosys, OpenROAD, Verilator and cocotb so LLM agents or engineers can take a design from spec to layout. Apache-2.0.
- BPM
- 140
- GRADE
- S
- LEVEL
- 4
- RELEASES
- 0
- YEARS
- 2026–2026
Spec To Layout
In August 2026 I started ChipForge, a plan for taking a chip from a written spec to a physical layout with agents doing most of the driving.
It's a uv workspace of Python packages, one per stage: forge-spec, hdl, verify, synth, pnr, data, agents, cli, dashboard. Underneath it wraps the open silicon tools that already exist: Yosys for synthesis, OpenROAD for place and route, Verilator and cocotb for verification. It's Apache-2.0, which is different from almost everything else I wrote that year, which went out under Pay It Forward.
By the end of the first day I had gate level simulations of an ALU and a counter running, the hello world of hardware. So far it's a scaffold with two toy circuits showing the pipeline connects end to end.
I started it because every stage in that flow is text going into a tool that spits out more text, checked by a tool that says yes or no. That seemed like a good fit for a language model with a verifier behind it.